/*
 * File: explicitinvocation_atomicsubsys.h
 *
 * Code generated for Simulink model 'explicitinvocation_atomicsubsys'.
 *
 * Model version                  : 3.0
 * Simulink Coder version         : 9.5 (R2021a) 14-Nov-2020
 * C/C++ source code generated on : Wed Jan  5 11:30:48 2022
 *
 * Target selection: ert.tlc
 * Embedded hardware selection: Intel->x86-64 (Windows64)
 * Code generation objectives:
 *    1. Execution efficiency
 *    2. RAM efficiency
 * Validation result: Not run
 */

#ifndef RTW_HEADER_explicitinvocation_atomicsubsys_h_
#define RTW_HEADER_explicitinvocation_atomicsubsys_h_
#ifndef explicitinvocation_atomicsubsys_COMMON_INCLUDES_
#define explicitinvocation_atomicsubsys_COMMON_INCLUDES_
#include "rtwtypes.h"
#endif                    /* explicitinvocation_atomicsubsys_COMMON_INCLUDES_ */

/* Model Code Variants */

/* Macros for accessing real-time model data structure */

/* Forward declaration for rtModel */
typedef struct tag_RTM RT_MODEL;

/* Block signals and states (default storage) for system '<Root>' */
typedef struct {
  real_T TmpRTBAtRate2sOutport1;       /* '<Root>/Rate2s' */
  real_T Integrator_DSTATE;            /* '<S2>/Integrator' */
  real_T TmpRTBAtRate2sOutport1_Buffer0;/* synthesized block */
} DW;

/* External inputs (root inport signals with default storage) */
typedef struct {
  real_T In1_1s;                       /* '<Root>/In1_1s' */
  real_T In2_2s;                       /* '<Root>/In2_2s' */
} ExtU;

/* External outputs (root outports fed by signals with default storage) */
typedef struct {
  real_T Out1;                         /* '<Root>/Out1' */
  real_T Out2;                         /* '<Root>/Out2' */
} ExtY;

/* Real-time Model Data Structure */
struct tag_RTM {
  /*
   * Timing:
   * The following substructure contains information regarding
   * the timing information for the model.
   */
  struct {
    struct {
      uint8_T TID0_1;
    } RateInteraction;
  } Timing;
};

/* Block signals and states (default storage) */
extern DW rtDW;

/* External inputs (root inport signals with default storage) */
extern ExtU rtU;

/* External outputs (root outports fed by signals with default storage) */
extern ExtY rtY;

/* Model entry point functions */
extern void explicitinvocation_atomicsubsys_initialize(void);
extern void explicitinvocation_atomicsubsys_step0(void);
extern void explicitinvocation_atomicsubsys_step1(void);

/* Real-time Model object */
extern RT_MODEL *const rtM;

/*-
 * The generated code includes comments that allow you to trace directly
 * back to the appropriate location in the model.  The basic format
 * is <system>/block_name, where system is the system number (uniquely
 * assigned by Simulink) and block_name is the name of the block.
 *
 * Use the MATLAB hilite_system command to trace the generated code back
 * to the model.  For example,
 *
 * hilite_system('<S3>')    - opens system 3
 * hilite_system('<S3>/Kp') - opens and selects block Kp which resides in S3
 *
 * Here is the system hierarchy for this model
 *
 * '<Root>' : 'explicitinvocation_atomicsubsys'
 * '<S1>'   : 'explicitinvocation_atomicsubsys/Rate1s'
 * '<S2>'   : 'explicitinvocation_atomicsubsys/Rate2s'
 * '<S3>'   : 'explicitinvocation_atomicsubsys/Rate1s/SS1'
 * '<S4>'   : 'explicitinvocation_atomicsubsys/Rate1s/SS2'
 */
#endif                       /* RTW_HEADER_explicitinvocation_atomicsubsys_h_ */

/*
 * File trailer for generated code.
 *
 * [EOF]
 */
